1. Field of the Invention
The present invention relates to a wavelength division multiplexing (WDM) system, and more particularly, to a channel allocation apparatus of an optical supervisory channel unit (OSU) in the WDM system.
2. Description of the Background Art
FIG. 1 is a schematic view of the WDM system.
As shown in FIG. 1, a multiplexer 10 multiplexes a plurality of optical signals each having a different wavelength (λ1, . . . , λn), and an optical amplifier 12 amplifies the multiplexed optical signal to a certain level.
An optical supervisory channel unit (OSU) 14 outputs an optical signal which has assigned a data channel and a voice channel required for managing a network.
An optical coupler 16 couples the optical signals of the optical amplifier 12 and of the OSU 14 and transmits the coupled signal to a destination. These 20 elements constitute an optical transmitting unit.
In general, the OSU provides a data communication and an orderwire (OW) channel between a WDM system-based systems such as a WDM terminal, a repeater or an optical add-drop multiplexer (OADM), and is roughly classified into a structure using an STM-1 (155.520 Mbps) and a structure using an E1 (2.048 Mbps).
FIG. 2 shows an example of a conventional OSU 100 using the STM-1.
As shown in FIG. 2, the OSU 100 includes an optical signal converter 20, an STM-1 framer 22, an FPGA (Field Programmable Gate Array) 24, a backboard connector 26 and a microprocessor 28.
The optical signal converter 20 performs a conversion operation between a STM-1 frame data and an optical signal. The STM-1 framer 22, implemented as an application specific IC (ASIC), allocates/extracts a data communication channel data (DCCD) and an orderwire data (OWD) to/from an overhead of the STM-1 frame data as well as framing/reframing the STM-1.
The FPGA 24 temporarily stores a DCCD, an OWD, a DCC clock signal (DCCCK), an OW clock signal (OWCK) and a frame pulse (OWFP), and the backboard connector 26 connects an external data processing unit (not shown) and the OSU 100.
As shown in FIG. 3, the STM-1 framer 22 consists of a framer 121 forming an STM-1 frame, an overhead inserting unit 122 for inserting an outputted DCCD and OWD outputted from the FPGA 24 into the overhead of the formed STM-1 frame, an overhead detecting unit 123 for extracting the STM-1 frame, the DCCD and the OWD from the received STM-1 frame data, and a reframer 124 for reframing the STM-1 frame extracted from the overhead detecting unit 123.
The operation of the OSU 100 using the conventional STM-1 frame constructed as described above will now be explained.
First, the DCCD, OWD, clock signals (DCCCK, OWCK) and the OWFP inputted from an external data processing unit (not shown) through the backboard connector 26 is stored in the FPGA 24.
After forming the STM-1 frame, the STM-1 framer 22 inserts the DCCD and the OWD into the overhead of the STM-1 frame under the control of the microprocessor.
That is, as shown in FIG. 3, the framer 121 of the STM-1 framer 22 forms an STM frame, and the overhead inserting unit 122 inserts the DCCD and the OWD outputted from the FPGA 24 into the overhead of the STM-1 frame under the control of the microprocessor 28.
Then, the optical signal converter 20 converts the STM-1 frame data outputted from the overhead inverting unit 122 into an optical signal by using a 155 M laser diode (not shown) and outputs the optical signal to the WDM system.
Meanwhile, the optical signal transmitted from the WDM system is converted into an STM-1 frame data by the optical signal converter 20, and the overhead detecting unit 123 of the STM-1 framer 22 detects an overhead of the STM-1 frame data under the control of the microprocessor 28 and outputs the DCCD, the OWD, the clock signal and the OWFP to the FPGA 24, and the STM-1 frame to the reframer 124.
Accordingly, the DCCD, the OWD, the clock signal and the OWFP inputted to the FPGA 24 are outputted to the external data processing unit (not shown) through the backboard connector 26, and the reframer 124 reframes the inputted STM-1 frame.
The OSU using the STM-1 implements the STM-1 framer which frames/reframes the STM-1 signal and extracts/inserts the DCCD and the OWD as the ASIC and interworks with the external data processing unit through the FPGA and the backboard connector.
FIG. 4 is a conventional OSU 200 using an E1.
As shown in FIG. 4, the conventional OSU 200 using the E1 consists of an optical signal converter 30, an E1 framer 32, a time slot interface (TSI) 34, a backboard connector 36 and a microprocessor 38.
The E1 framer 32 frames an E1 frame data to a time slot data under the control of the microprocessor 38, and the TSI 34 interfaces the time slot data of the E1 framer 32 in a time division multiplexing (TDM) method according to a control signal outputted from the microprocessor 38 and extracts a DCCD and an OWD.
In addition, the TSI 34 interfaces the DCCD and the OWD inputted from an external data processing unit (not shown) through the backboard connector 36 by the TDM method to input them into the time slot data, and outputs them to the E1 framer 32.
In this manner, when the E1 framer 32 and the TSI 34 are used, the E1 framer 32 performs an E1 framing/reframing and the TSI 34 separates a channel, and forms corresponding channels as a serial data according to a use and transmits them to the backboard connector 36.
However, the conventional OSU using the STM-1 uses the STM-1 framer chip and the 155M laser diode for a low rate data, a cost charge is increased. Especially, since the STM-1 framer interworks with the microprocessor, much time is taken for the performance implementation, the board testing, and the like.
In addition, in the OSU using the E1, the commercial chips that generally handle the DS-1E such as the TSI follows a coding method such as an AMI and an HDB3. Accordingly, the commercial chip such as the TSI is not suitable to be used for an optical communication system on the basis of a Manchester code and an NRZ signal in a physical layer, and especially, for the low rate data.
This is resulted from unnecessary functions as well as from a difference in the interface method. If the OSU using the conventional E1 is implemented by using the commercial chip, much time is taken for implementing a function, and operating chips such as a processor are required to designate an address.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.